The present invention relates to a control circuit of a memory system including a dynamic random access memory (hereinafter referred to as a DRAM) as a memory element, and more particularly to a circuit configuration of an integrated circuit suited for a case in which the control circuit of the DRAM is constituted of a plurality of integrated circuits.
Generally, in order to make access to a desired address of the DRAM, a memory address signal includes a row address signal and a column address signal. That is, an address is specified by the row address and the column address. A row address strobe (RAS) signal and a column address strobe (CAS) signal are generated by a control circuit with a predetermined time relation to the address signal. The row address strobe signal indicates a read-out timing of the row address signal and the column address strobe signal indicates a read-out timing of the column address signal. The control circuit also generates a write enable (WE) signal for indicating whether a memory access request signal supplied externally to the control circuit indicates the writing or reading operation.
Japanese Unexamined Patent Publication JP-A-62-252591 filed Apr. 24, 1986 by Seiko Electronic Industry Co., Ltd. discloses that RAS, CAS and WE signals of the control signals are generated by a timing controller and a memory address is generated by an LSI circuit different from an LSI circuit including the timing controller in response to an instruction of the timing controller.
Further, the DRAM is connected to a data bus through a bus gate for transmission and reception of data. When detection and correction of error in data are made, a circuit for the detection and correction of errors is additionally provided between the DRAM and the bus gate.
In the technique disclosed in the above publication, the timing controller and the address controller of the DRAM control circuit are constituted of different LSI chips, respectively. Thus, differences in a signal propagation time occur between the RAS signal and the CAS signal of the control signals in the timing controller circuit and the row address signal and the column address signal in the address control circuit due to scattered characteristics in the manufacture of the LSI chips. Accordingly, in order to absorb the variations of signal propagation time between the different LSI chips, it is necessary to add sufficient margins to the respective time relations between the RAS signal and the row address signal and between the CAS signal and the column address signal. This causes increased access time and cycle time of the memory by the added margin. At the same time, there is a problem that a rising of the RAS signal and the CAS signal is retarded due to delay of the control signal in a signal path between the LSI chip for the timing control and the LSI chip for the address control.
When a memory bank is increased, the number of components is greatly increased so that a reduction in reliability occurs.
In order to solve the above problems, one may consider incorporating all functions of the control circuit of the DRAM into a single LSI chip. However, this is not practical in view of the remarkably increased number of pins of the LSI chip and a cost thereof.